library verilog;
use verilog.vl_types.all;
entity dbg_trace is
    generic(
        Tp              : integer := 1
    );
    port(
        Wp              : in     vl_logic_vector(10 downto 0);
        Bp              : in     vl_logic;
        DataIn          : in     vl_logic_vector(31 downto 0);
        OpSelect        : out    vl_logic_vector(2 downto 0);
        LsStatus        : in     vl_logic_vector(3 downto 0);
        IStatus         : in     vl_logic_vector(1 downto 0);
        RiscStall_O     : out    vl_logic;
        Mclk            : in     vl_logic;
        Reset           : in     vl_logic;
        TraceChain      : out    vl_logic_vector(39 downto 0);
        ContinMode      : in     vl_logic;
        TraceEnable_reg : in     vl_logic;
        WpTrigger       : in     vl_logic_vector(10 downto 0);
        BpTrigger       : in     vl_logic;
        LSSTrigger      : in     vl_logic_vector(3 downto 0);
        ITrigger        : in     vl_logic_vector(1 downto 0);
        TriggerOper     : in     vl_logic_vector(1 downto 0);
        WpQualif        : in     vl_logic_vector(10 downto 0);
        BpQualif        : in     vl_logic;
        LSSQualif       : in     vl_logic_vector(3 downto 0);
        IQualif         : in     vl_logic_vector(1 downto 0);
        QualifOper      : in     vl_logic_vector(1 downto 0);
        RecordPC        : in     vl_logic;
        RecordLSEA      : in     vl_logic;
        RecordLDATA     : in     vl_logic;
        RecordSDATA     : in     vl_logic;
        RecordReadSPR   : in     vl_logic;
        RecordWriteSPR  : in     vl_logic;
        RecordINSTR     : in     vl_logic;
        WpTriggerValid  : in     vl_logic;
        BpTriggerValid  : in     vl_logic;
        LSSTriggerValid : in     vl_logic;
        ITriggerValid   : in     vl_logic;
        WpQualifValid   : in     vl_logic;
        BpQualifValid   : in     vl_logic;
        LSSQualifValid  : in     vl_logic;
        IQualifValid    : in     vl_logic;
        ReadBuffer      : in     vl_logic;
        WpStop          : in     vl_logic_vector(10 downto 0);
        BpStop          : in     vl_logic;
        LSSStop         : in     vl_logic_vector(3 downto 0);
        IStop           : in     vl_logic_vector(1 downto 0);
        StopOper        : in     vl_logic_vector(1 downto 0);
        WpStopValid     : in     vl_logic;
        BpStopValid     : in     vl_logic;
        LSSStopValid    : in     vl_logic;
        IStopValid      : in     vl_logic
    );
end dbg_trace;
